1. Field of the Invention
The present invention relates to testing of semiconductor integrated circuits. More particularly, the present invention relates to testing of redundant integrated circuit dies formed on semiconductor wafers.
2. Description of The Prior Art and Related Information
An important step in integrated circuit manufacture is testing of the individual integrated circuit dies after fabrication. Typically a large number of separate integrated circuit dies are fabricated on a single semiconductor wafer as illustrated in FIG. 1. The integrated circuit dies are separated by dicing lanes on the wafer, as illustrated in FIG. 1, and after fabrication of the integrated circuits the wafer is sawed along the dicing lanes to form the individual integrated circuit dies. After the dies are separated, individual testing of the dies may take place. Alternatively, the individual dies on the wafer may be serially tested before sawing the wafer along the dicing lanes.
The conventional prior art approach to testing redundant integrated circuit dies involves mechanical probe testing of the individual dies. In this approach each individual die is tested by placing a set of mechanical probes in physical contact with the bonding pads on the die, one die at a time in serial fashion. Upon making electrical contact with the bonding pads on the die, the die is stimulated by applying voltages to appropriate input pads and resultant output electrical signals are measured on the output pads. In some applications, integrated circuit dies which pass the initial mechanical probe testing need to be further tested in specific operating conditions. For example, in testing integrated circuit chips used as readout chips in infrared focal plane arrays, the integrated circuit dies which pass the mechanical probe testing often need to be cryogenically tested at extremely low temperatures. Such cryogenic testing is not readily accomplished with simple mechanical probe testing and each die must be individually wire bonded into a temporary package compatible with the cryogenic test procedure.
The prior art mechanical probe testing testing procedure described above has a number of disadvantages. First of all, the mechanical probe testing requires potentially damaging, temporary electrical connections to be made with the wire bond pads of each integrated circuit die. These same wire bond pads often need to be used for wire bonding the dies which pass the probe testing and the probe damage often precludes the die from passing quality inspection. This results in loss of yield. Additionally, the mechanical alignment and moving of the probes from one integrated die to the next is quite time consuming. The alignment of the probe on the individual dies so as to be positioned accurately on the easily damaged wire bond pads is inherently a very time consuming process. Indeed, due to the time consuming nature of testing integrated circuit dies, the costs of testing after processing are typically a greater factor in integrated circuit die production than the materials costs. A further disadvantage of the mechanical probe test procedure is the high electrical noise created at the probe/die interface. For integrated circuit applications requiring very low noise characteristics, such as the infrared focal plane array readout applications described above, such a temporary electrical connection is frequently incompatible with the low noise requirements of the device. Also, the mechanical probing is incompatible with testing in nonambient environments such as cryogenic environments.
The alternative to mechanical probing, wire bonding, also suffers from a number of disadvantages. First of all the process is even more time consuming than the mechanical probe test procedure described above. Also, the approach requires redundant wire bonding pads on the integrated circuit die since after testing the test wire bonds need to be removed to allow final assembly of the die. After removing the wire bonds, the wire bond pads are too damaged, however, to allow for a second wire bonding and therefore redundant wire bonds are necessary. For these reasons, the wire bonding test procedure is very expensive.
Accordingly, a need presently exists for a relatively fast and inexpensive system and method for testing redundant integrated circuit dies. In particular, a need for low noise testing of redundant integrated circuit dies presently exists for applications involving cryogenic low noise integrated circuit devices such as infrared focal plane array readout integrated circuits.